在我加入 Semtech 的九年里，传输线脉冲 (TLP) 基础知识一直是新员工和客户最重要的培训主题之一。许多人问我们为什么总是强调 TLP 分析的重要性并广泛依赖它为我们的客户提供最佳解决方案。TLP 测试无法提供与行业标准（如 IEC 61000-4-2 或 ESDA/JEDEC JS-001）的规定完全相同的波形。它不保证 IC 或系统能通过所需静电放电 (ESD) 测试级别的抗扰性测试。始终建议在 TLP 测试完成后使用 ESD 发生器验证所有结果。那么，为什么我们不直接全部用 ESD 发生器进行测试？毕竟大多数工程师更熟悉和普遍接受 ESD 发生器。要回答这个问题，我认为务必要理解 TLP 不是 IEC 测试的替代或升级，而是作为一种分析工具对 ESD 枪测试进行补充。ESD 枪测试能告诉我们行或不行，但 TLP 可以帮助我们了解为什么和怎样优化。
In recent years, TLP has become widely accepted and has been adopted by most of our customers globally. Its results have become one of the most important parameters for evaluating both component and system level ESD. Here are some tips on how TLP can be utilized as an analysis tool.
Transient Breakdown and Turn on Characteristics
The first step in selecting the ideal transient voltage suppressor (TVS) protection device is the identification of working voltage (VRWM ) and breakdown voltage (VBR ). The VRWM guarantees that TVS will stay at the OFF stage at or below the working voltage. TVS breakdown, snapback and holding voltage/current, can show when exactly the TVS switches between ON and OFF state. These are often tested with DC source with current in mA range and can be found on most datasheets for diodes. However, TVS diodes are designed to protect against transient threats, which have a pulse duration in ns to µs range. The TLP test specifies a 100ns pulse width. This pulse width more closely approximates real world ESD transients from a timing standpoint. Depending on the TVS technology, both rise time and pulse duration can have a large impact on these turn on characteristics.
Figure 1: TLP comparison between different technologies
Semtech offers different TVS technologies to meet the needs for different applications. TLP comparison in Figure 1 shows the behavior of different types of TVS in the breakdown region. In general, snapback devices with lower breakdown voltage or holding voltage usually offer better clamping voltage, but these devices can potentially cause latch-up when a biased voltage is present at the protected line.
Dynamic Resistance (RDYN)
In an ideal world, a TVS will turn on at the breakdown voltage and then provide a SHORT path to conduct all transient energy away to GND. But in reality, the TVS will exhibit certain dynamic resistance after it starts to conduct. This resistance is usually in the mΩ range. Dynamic resistance (Figure 2), which is the slope of the IV curve, can tell how much your clamping voltage will vary when the current is increased. This is usually defined between 4A to 16A of device under testing (DUT) current, which is approximately the range of 2kV to 8kV in IEC pulse at 30ns.
Figure 2: Dynamic resistance
Most ESD protection datasheets only include the clamping voltage waveform taken at 8kV with ESD generator, or some engineers only use the 8kV clamping waveform to select a device. Figure 3 is an example to show how we can compare two devices with different RDYN. TVS B with the higher dynamic resistance will exhibit high clamping after the cross point of the two curves, but still can provide a better clamping at lower levels. Since this crossing point can be at any level when comparing devices, the 8kV clamping graph may be only relevant at 8kV, but it’s not sufficient information for other levels. For example, in today’s high-speed applications where some data lines still struggle to pass even 2kV at system level, the dynamic resistance then becomes very critical. In other words, lower 8kV clamping voltage doesn’t always guarantee lower clamping voltages at all levels. On the other hand, the TVS with lower dynamic resistance can provide better clamping voltage even when its breakdown voltage is higher. One simple TLP IV curve with dynamic resistance can help to estimate if the clamping is low enough for the target levels.
Figure 3: TLP comparison for devices
System-Level Analysis –Who Is Protecting Whom?
Most ICs have some kind of internal ESD protection structures. These provide very minimal protection, if at all. However, during a transient event, the protection internal to the IC can be triggered and will compete with the external TVS for ESD current. The path which has lower clamping and faster response will conduct more current. Figure 4 shows an example on how this can be visualized with the TLP analysis.
Figure 4: Evaluation on effectiveness of TVS
A TLP test is usually done in three steps: first is to evaluate the IC without any protection (black curve) to find its threshold. In this case, the IC failed around 13V and 8A. The second step is to evaluate the TVS (green curve), which will show how well TVS can protect the IC before you put it on the PCB. In this case, it takes about 16A for this TVS to reach to 13V which is the failure threshold of the IC; this indicates that the TVS will exhibit lower clamping than IC’s internal protection until at least 16A. The final step is to evaluate the combination of the IC and the TVS (blue curve). As shown in Figure 4, the IV curve follows the IC before the TVS’s breakdown voltage. And after the TVS turns on, both the IC and the TVS will be conducting current, but the overall IV curve will mainly follow the TVS, since the TVS provides the path with much lower impedance. The combination of internal protection and TVS can bring this failure threshold to at least 24A. If the TLP result shows that the internal protection circuitry clamps to a lower voltage than the TVS, or begins conducting even before the TVS can turn on, then the IC is “protecting” the TVS instead.
Consistency and Repeatability
Other advantages of the TLP analysis which make it to be an important analysis tool are the consistency of the waveform and high repeatability of the test results. It’s not uncommon to see dramatically different test results between test labs or test setups, especially during air discharge tests due to wider tolerances of ESD waveforms specified in standards and the complexities of ESD coupling path. Slight differences in test setup or test procedures can cause major differences in test results. With a well-defined 50Ω system, TLP testing delivers consistent and controlled waveforms to the DUT, which is very crucial for debugging and analysis. This also makes detecting any waveform distortion and the calibration process much faster and easier than IEC standard calibration.
Transmission line pulse testing is an important analysis tool when designing and evaluating system ESD protection. While it doesn’t perfectly correlate to industry ESD standards, it provides a very close first approximation by allowing comparison of internal IC protection structures to external TVS devices. This type of analysis can save time and money in the long run for designing system level ESD robustness. Semtech’s team of application engineers can aid in TLP analysis and System Efficient ESD Design (SEED) and help customers choose a protection scheme that works seamlessly in their system.
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